Implantable stimulation devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder sublaxation, etc. The present invention may find applicability in all such applications, although the description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227 (“the '227 patent”), issued Feb. 4, 2003 in the name of Paul Meadows et al., which is incorporated herein by reference in its entirety.
Spinal cord stimulation is a well-accepted clinical method for reducing pain in certain populations of patients. As shown in FIG. 1, a SCS system typically includes an Implantable Pulse Generator (IPG) 100, which includes a biocompatible case 116 formed of titanium for example. The case 116 holds the circuitry and power source or battery necessary for the IPG to function. The IPG 100 is coupled to electrodes 106 via one or more electrode leads (two such leads 102 and 104 are shown), such that the electrodes 106 form an electrode array 110. The electrodes 106 are carried on a flexible body 108, which also houses the individual signal wires 112, 114, coupled to each electrode. The signal wires 112, 114 are in turn connected to the IPG 100 by way of an interface 115, which allows the leads 102 and 104 to be removably connected to the IPG 110. Exemplary connector arrangements are disclosed in U.S. Pat. Nos. 6,609,029 and 6,741,892, which are incorporated herein by reference. In the illustrated embodiment, there are eight electrodes on lead 102, labeled E1-E8, and eight electrodes on lead 104, labeled E9-E16, although the number of leads and electrodes is application specific and therefore can vary.
The electrode array 110 is typically implanted along the dura of the spinal cord, and the IPG 100 generates electrical pulses that are delivered through the electrodes 106 to the nerve fibers within the spinal column.
Further details concerning the structure and function of typical IPGs, as well as IPG systems including telemetry and powering/recharging details, are disclosed in many of the documents incorporated by reference into this disclosure, with which the reader is assumed familiar.
An IPG 100 may include current source/sink circuitry that is configured to supply/receive stimulating current to/from the electrodes 106 on the IPG, and ultimately to/from tissue. For example, FIG. 2 shows an exemplary current source 500 and a corresponding current sink 501 used to stimulate tissue, exemplified generically as a load 505 (R). As one skilled in the art will understand, transistors M1 and M3 in the current source 500, and transistors M2 and M4 in the current sink 501, comprise a current mirror. However, other current source or sink circuitry can be used, such as that disclosed in U.S. patent application Ser. No. 11/138,632 (“the '632 application”), filed May 26, 2005, which is incorporated herein by reference in its entirety.
Both the source 500 and sink 501 are coupled to a current generator 506 configured to generate a reference current, Iref. A suitable reference current generator is disclosed in U.S. Pat. No. 6,181,969 (“the '969 patent”), issued Jan. 30, 2001 in the name of inventor John C. Gord, which is incorporated herein by reference in its entirety. The reference current in both the current source/sink 500/501 is input into a digital-to-analog converter (DAC) configured to regulate the current that is sourced to or sunk from the load 505. Thus, source circuitry 500 employs DAC circuitry 502, while sink circuitry 501 employs DAC circuitry 503.
DAC circuitry 502, 503 is configured to regulate and/or amplify Iref and to output an output current Iout. Specifically, the relation between Iout and Iref is determined in accordance with input control bits arriving on busses 513, 513′, which gives DAC circuitry 502, 503 its digital-to-analog functionality. Essentially, in accordance with the values of the various M control bits on bus 513, any number of output stages (i.e., transistors M1, M2) are tied together in parallel such that Iout can range from Iref to 2M*Iref in increments of Iref, as will be explained in further detail later with reference to FIG. 4.
As shown in FIG. 2 for simplicity, current source circuitry 500 is coupled to an electrode EX on the IPG device 100, while current sink circuitry 501 is coupled to a different electrode EY on the IPG device. However, in accordance with the approach disclosed in the '969 patent, each electrode on the device is actually hard-wired to both an current source 500 and an current sink 501, only one (or neither) of which is activated at a particular time to allow the electrode to selectively be used as either a source or sink (or as neither). This is shown in FIG. 3, which shows four exemplary electrodes E1, E2, E3, and E4, each having their own dedicated and hard-wired current source 500 and sink 501 circuitry. A primary clinical benefit of having the ability control current on each electrode is that it allows precise shaping of the electric field used for stimulation from the array of electrodes. Systems without this ability have less control of the field and are subject to variations and changes in impedance among electrodes.
The current source 500 and sink 501 circuitry hard-wired at each electrode are sometimes respectively referred to as PDACs and NDACs, reflecting the fact that the sources 500 are typically formed of P-type transistors while the sinks 501 are typically formed of N-type transistors. The use of transistors of these polarities is sensible given that the source is biased to a high voltage (V+), where P-type transistors are most logical, while the sink is biased to a low voltage (V−), where N-type transistors are most logical, as shown in FIG. 2. The substrate connection (not shown) for the transistors would typically be tied to the appropriate power supply, either V+ or V−, but could also be tied to the transistors' sources.
As shown in FIG. 3, the current sources (PDACs) and sinks (NDACs) active at any given time can be programmed. Thus, as shown, the source circuitry at electrode E2 on the IPG is currently active, while the sink circuitry at electrode E3 is also currently active. At a later time, electrodes E2 and E3 could be switched such that E2 now operates as the sink, while E3 operates as the source, or new sources or sinks could be chosen, etc., depending on how the logic in the IPG is programmed in accordance with optimal therapy for the patient in which the IPG is implanted.
A consequence of this architecture is that, as mentioned, each electrode has its own dedicated source (i.e., PDAC) and sink (i.e., NDAC) circuitry. Further details of such dedicated current source circuitry 500 for a particular electrode (e.g., EX) as disclosed in the '969 patent is shown in FIG. 4. Dedicated current sink circuitry 501 for each electrode, similar to the current source circuitry 500 but differing in polarity (see e.g., FIG. 2), would likewise be hardwired to the electrode EX, but is not shown for convenience in FIG. 4. (However, both the source and sink circuitry are shown in a simplified manner in FIG. 7). Also not shown for convenience is the presence of a coupling capacitor typically hardwired at each electrode Ex (see '969 patent, FIG. 3, element 203).
The source circuitry of FIG. 4 can be programmed to output a source current of a particular magnitude. Specifically, the circuitry as shown is capable of outputting to the electrode Ex a current Iout ranging from Iref to 127Iref in increments of Iref, depending on the status of the control bits (Bit<1:M>). This occurs as follows: each control bit, when selected, contributes 2(M-1) worth of current to the output current, Iout, through activation of pass transistors 530 in each of the M stages that comprise the current source. For example, if a current of 53Iref is desired at Iout, control bits Bit<1, 3, 5, 6> would be enabled (active low) to turn on transistors 5301, 5303, 5305, and 5306, which respectively contribute Iref, 4Iref, 16Iref and 32Iref, in sum, 53Iref. Although each stage is shown as having its own current source Iref, it would usually be the case that each stage taps into a singular reference current (not shown for convenience), which is preferred to ensure current uniformity across the stages.
However, this current source/sink architecture of FIGS. 3 and 4 does not comprise an efficient use of space on the integrated circuit in the IPG on which the current source/sink circuitry is fabricated. In a typical SCS system implementation, the IPG might contain 16 electrodes, E1 through E16. However, it is usually the case that only one PDAC (source) and one NDAC (sink) are active at one time. Or, more rarely, four or more PDACs (sources) or NDACs (sinks) might be active at one time. Even in such an extreme case, it will be noted that the majority of the PDACs (source) and NDACs (sinks) are inactive. Furthermore, even for those electrodes that are active at a particular time, only one of the source 500 or sink 501 circuitry for that electrode can be active. The result is that, most of the time, most of the PDACs or NDACs in the IPG 100 are not being utilized. When one considers that the PDACs or NDACs take up significant space on the integrated circuit (see FIG. 4), the provision of such redundancy for every electrode seems inefficient.
Another current source/sink architecture is disclosed in the above-incorporated '227 patent, and in particular in FIG. 4A of the '227 patent, salient aspects of which are summarized in the present application in FIGS. 5 and 6. As shown in FIG. 5, the architecture of the '227 patent also uses a plurality of current sources and sinks, and further uses a low impedance switching matrix that intervenes between the sources/sinks and the electrodes EX. Notice that each source/sink pair is hard-wired together at nodes 333, such that the switching matrix intervenes between the common nodes 333 and the electrodes. Of course, only one of the source or the sink in each pair is activated at one time, and thus point 333 in any pair will source or sink current at any particular time. Through appropriate control of the switching matrix, any of the nodes 333 (and hence any of the PDAC/NDAC pairs) may be connected to any of the electrodes EX at any time.
While generally a suitable architecture, the architecture of FIGS. 5 and 6 suffer from drawbacks. For one, this architecture puts additional resistance—namely the resistance of the switches in the switching matrix—in the output path between the power supply in the DAC circuitry and the electrode. As explained in the above-incorporated '632 application, it is generally desired to minimize resistance between the power supply and the electrode. Thus, and referring to FIG. 6, which shows the architecture of FIG. 5 in further detail, it is desired that the resistance be minimized in the output path between the power supply V+ or V− and a given electrode EX. This is because any resistance in the output path will give rise to a voltage drop in the output path (the output path resistance times Iout) which is not otherwise useful in the context of the circuitry. But in the architecture of FIGS. 5 and 6, it can be seen that three elements are serially connected between the power supplies and the electrode: the current mirror, the bit select transistor, and the transistor (switch) in the low impedance switch matrix. Due to the additional resistances of these components, and specifically the additional resistance of the switches in the switch matrix, power (i.e., the output path resistance times Iout2) is wasted. In an implantable stimulator device, such unnecessary power loss is regrettable, because battery life in such devices is critical and beneficially made as long as possible.
Moreover, the architecture of FIGS. 5 and 6 is further inefficient from a layout perspective. Due to the common node 333 between a given PDAC source and NDAC sink pair, only one DAC in each pair can be active at any time. Thus, and like the architecture of FIGS. 3 and 4, DAC circuitry is guaranteed to go unused at any particular time. More specifically, at least 50% of the DAC circuitry (the unselected DAC in a pair), and likely more, will go unused at any given time, which again is a wasteful use of layout on the integrated circuit.
In short, the implantable stimulator art, or more specifically the IPG or SCS system art, would be benefited by an architecture that allows variable currents to be provided at a number of electrodes, but in a more space-efficient manner.
Additionally, such an improved architecture would also preferably allow for fine adjustments to the current to be sourced or sunk. In this regard, it has been recognized in the art that it can be beneficial to finely adjust the amount of current sourced or sunk at a particular electrode in increments less than Iref. For example, in the above-reference '969 patent, and as shown here in FIG. 7, it is disclosed that the source/sink circuitry 500/501 can include a stage or stages 550 which provide a fraction of the reference current, Iref. These stages 550, are controlled by another control bit, Bit<0> (designated as “0+” for the source and “0−” for the sink). Specifically, it is noted in the '969 patent that fractional values of (½)m (i.e., ½*Iref, ¼*Iref, ⅛*Iref, etc.) or 1/m (e.g., ½*Iref, ⅓*Iref, etc.), or multiple values thereof, can be provided by stage or stages 550. See '969 patent, col. 6, l. 43 to col. 7, l. 6.
By providing the ability to include fractions of the reference current, Iref, in the overall current, fine adjustments (via stages 550) can be made to the otherwise coarse current adjustments provided by the remainder of the circuitry. However, the overall result is still one which is not terribly space efficient, because, as noted above, much of the current source and sink circuitry is guaranteed to be unused at any given time.